With the slowing of Moore’s Law, the industry is adopting a variety of advanced packaging methods to further advance integration and performance roadmaps. Whether it be Intel’s Foveros, TSMC’s Integrated Fanout, or the DRAM industry’s High Bandwidth Memory (HBM), these new architectures are rapidly changing the role of wafer test in the semiconductor manufacturing process. In particular, since IC’s now become a heterogenous assembly of individual die, the required test coverage for each die to ensure an economically-viable final-assembly yield is much higher, resulting in far more stringent wafer-test specifications and longer test times than in classical monolithic-die wafer sort. Together, these result in electromechanical interfaces becoming smaller and more dense, AC and DC electrical performance requirements advancing far beyond yesterday’s wafer sort specifications; and a need for rapid improvement of productivity and cost-of-ownership. We’ll explore a few examples and discuss what the test community can do to support of this exciting new direction for industry innovation.