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Godwin Maben

Synopsys Scientist
Synopsys

Godwin Maben started his EDA career developing low power design flow methodology after a semiconductor career designing power-sensitive USB/FireWire(1394) devices during the evolution of these standards back in the 1990’s. At Synopsys, Godwin has been instrumental in first time silicon deployment of various low power architectures such as Power Gating/Retention Schemes/Zero Pin Retention flops/Well Biasing as well as DVFS/AVFS architectures. He has also defined many specifications for the automation of most low power sensitive designs and was involved in the standardization process for UPF. Godwin’s current research interests include accurate power analysis methodology, with detailed focus on glitches to address the high demands of current datapath oriented designs.

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